1. Technical Field
Various embodiments relate to a semiconductor apparatus, and more particularly, to a voltage generation circuit of a phase change RAM (random access memory).
2. Related Art
In general, the unit cell of a phase change random access memory (PCRAM) is constituted by one switching element connected to a word line, for example, a diode, and a variable resistor (GST: Ge2Sb2Te5) connected to a bit line. The PCRAM can store data in a memory cell by controlling a reversible phase change of the variable resistor (GST). The reversible phase change of the variable resistor (GST) is implemented by Joule heating through the electrical pulse applied from an outside.
FIG. 1 is a circuit diagram of a conventional PCRAM 1.
The PCRAM 1 includes a latch unit 10, a read unit 20, a write unit 30, a global bit line switch 40, and a plurality of bit line switches 50, 51 and 52. FIG. 1 also illustrates the GYSWN, GYSWP, LYSWN and LYSWP signals.
The latch unit 10 exchanges data DQ with the read unit 20 and the write unit 30 in response to a latch activation signal LEN. The latch activation signal LEN is a signal which is activated in response to a write or read command for input and output of the data DQ.
The PCRAM 1 exchanges data with a memory cell through a global bit line GBL and bit lines BL when performing a read or write operation. Therefore, the global bit line switch 40 and the plurality of bit line switches 50, 51 and 52 electrically connect the read unit 20 or the write unit 30 with the memory cell in the read or write operation of the PCRAM 1.
The PCRAM 1 reads or writes the data DQ to and from the memory cell by using different voltages. That is to say, the PCRAM 1 performs the read operation using a voltage level which does not change the phase of the memory cell, and performs the write operation using a voltage level which changes the phase of the memory cell. Since the phase change of the memory cell is generally implemented through Joule heating, a first power supply voltage VPP inputted to the write unit 30 is higher than a second power supply voltage VDD inputted to the read unit 20.
In the case where the PCRAM 1 is driven by a high voltage after being driven by a low voltage, the PCRAM 1 discharges the global bit line GBL and the bit lines BL to secure operational reliability. In general, in the PCRAM 1, a pre-read operation for preventing an unnecessary write operation before a program operation when the write operation is started and a verify-read operation for verifying whether the write operation is precisely performed are performed. Therefore, it is necessary to discharge the global bit line GBL and the bit lines BL before the program operation.
However, a phenomenon occurs, where junction capacitors are formed between the plurality of bit line switches 50, 51 and 52 and the global bit line GBL and the voltage of a node to which the global bit line GBL and the plurality of bit line switches 50, 51 and 52 are connected drops below a discharge voltage. Due to this fact, a phenomenon is likely to occur, in which the first power supply voltage VPP applied to the write unit 30 drops.